MC9S08GT32CFDE Freescale Semiconductor, MC9S08GT32CFDE Datasheet - Page 274

• Manufacturer Part Number: MC9S08GT32CFDE
• Description: IC MCU 32K FLASH 20MHZ 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT32CFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Controller Family/series: HCS08
• No. Of I/o's: 39
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix A Electrical Characteristics
1
2
3
4
A.9.2
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
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This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f
on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
Timer/PWM (TPM) Module Timing
RESET PIN
Figure A-12. Active Background Debug Mode Latch Timing
BKGD/MS
RESET
DD
IRQ
and 80% V
MC9S08GB/GT Data Sheet, Rev. 2.3
Figure A-11. Reset Timing
Figure A-13. IRQ Timing
t
MSSU
DD
levels. Temperature range –40°C to 85°C.
t
ILIH
t
extrst
t
MSH
Self_reset
and then samples the level
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