DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 1035

• Manufacturer Part Number: DF2378BVFQ35V
• Description: IC H8S/2378 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes:
1. The active or halted state can be selected by means of the MSTP0 bit in MSTPCR.
2. Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
3. TDR, SSR, and RDR are halted (reset) and other registers are halted (retained).
4. BC2 to BC0 are halted (reset) and other registers are halted (retained).
Notes: •
Halted (Retained) in the table means that internal register values are retained and
internal operations are suspended.
Halted (Reset) in the table means that internal register values and internal states are
initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
: Transition after exception handling
•
1. NMI, IRQ0 to IRQ15, 8-bit timer interrupts, watchdog timer interrupts.
2. NMI, IRQ0 to IRQ15
Program execution state
SCK2 to
SCK0 = 0
From any state, a transition to hardware standby mode occurs when STBY is driven low.
From any state except hardware standby mode, a transition to the reset state occurs
when RES is driven low.
(8-bit timer interrupts are valid when MSTP0 = 0.)
(IRQ0 to IRQ15 are valid when the corresponding bit in SSIER is 1.)
(Internal clock is PLL
circuit output clock)
High-speel mode
Clock division
Reset state
mode
RES pin = high
SCK2 to
SCK0 ≠ 0
Figure 24.1 Mode Transitions
STBY pin = high
RES pin = low
SLEEP
instruction
Any interrupt
SLEEP
instruction
Interrupt
External
interrupt
SLEEP
instruction
: Power- down mode
*2
*1
Rev.7.00 Mar. 18, 2009 page 967 of 1136
MSTPCR =
H'FFFF (H'FFFE),
EXMSTPCR = H'FFFF,
SSBY = 0
module-clocks-stop
Program-halted state
STBY pin = low
SSBY = 0
SSBY = 1
standby mode
standby mode
Sleep mode
Section 24 Power-Down Modes
Hardware
Software
mode
All
REJ09B0109-0700