DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 948
![IC H8S/2378 MCU FLASH 144-LQFP](/photos/12/29/122922/df2378bvfq35v_sml.jpg)
DF2378BVFQ35V
Manufacturer Part Number
DF2378BVFQ35V
Description
IC H8S/2378 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2378BVFQ35V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 21 Flash Memory (0.18-μm F-ZTAT Version)
Table 21.4 Parameters and Target Modes
Name of
Parameter
Download pass
and fail result
Flash pass and
fail result
Flash
programming/
erasing frequency
control
Flash user branch
address set
Flash multi-
purpose address
area
Flash multi-
purpose data
destination area
Flash erase block
select
Note:
(1)
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM
area to be downloaded is the 128-kbyte area starting from the address specified by FTDAR.
Download control is set in the program/erase interface register, and the return value is passed
using the DPFR parameter.
(a) Download pass/fail result parameter (DPFR: single byte of start address specified by FTDAR)
This parameter indicates the return value of the download result. The value of this parameter can
be used to determine if downloading is executed or not. Since the confirmation whether the SCO
bit is set to 1 is difficult, the certain determination must be performed by writing the single byte of
the start address specified by FTDAR to the value other than the return value of download (for
example, H'FF) before the download start (before setting the SCO bit to 1).
Rev.7.00 Mar. 18, 2009 page 880 of 1136
REJ09B0109-0700
Download Control
* A single byte of the start address to download an on-chip program, which is specified by
FTDAR.
Abbrevia-
tion
DPFR
FPFR
FPEFEQ
FUBRA
FMPAR
FMPDR
FEBS
Down
Load
⎯
⎯
⎯
⎯
⎯
⎯
Initializa-
tion
⎯
⎯
⎯
⎯
Program-
ming
⎯
⎯
⎯
⎯
Erasure
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Alloca-
tion
On-chip
RAM *
R0L of
CPU
ER0 of
CPU
ER1 of
CPU
ER1 of
CPU
ER0 of
CPU
R0L of
CPU
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