DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 49

• Manufacturer Part Number: DF2378BVFQ35V
• Description: IC H8S/2378 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 6.76 Example of Idle Cycle Operation after DRAM Access
Figure 6.77 Example of Idle Cycle Operation after DRAM Access
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
Figure 6.83 Example of Timing when Write Data Buffer Function Is Used .............................. 269
Figure 6.84 Bus Released State Transition Timing .................................................................... 272
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface ........... 273
Section 7 DMA Controller (DMAC) .................................................................279
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Figure 7.7
Figure 7.8
Figure 7.9
Figure 7.10 Example of Single Address Mode Setting Procedure
Figure 7.11 Operation in Normal Mode ..................................................................................... 324
Figure 7.12 Example of Normal Mode Setting Procedure.......................................................... 325
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) ................................................. 327
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ................................................. 328
Figure 7.15 Operation Flow in Block Transfer Mode ................................................................ 329
Figure 7.16 Example of Block Transfer Mode Setting Procedure.............................................. 330
Figure 7.17 Example of DMA Transfer Bus Timing.................................................................. 331
Figure 7.18 Example of Short Address Mode Transfer .............................................................. 332
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) .......................................... 333
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode).......................................... 334
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) .......... 259
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)............................................ 260
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) ........................................................ 261
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2) ............ 262
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)...................... 263
Write Accesses to DRAM Space in RAS Down Mode ........................................... 266
and Write Accesses to Continuous Synchronous DRAM Space in RAS Down
Mode (SDWCD = 1, CAS Latency 2)..................................................................... 267
Block Diagram of DMAC ....................................................................................... 280
Areas for Register Re-Setting by DTC (Channel 0A) ............................................. 305
Operation in Sequential Mode................................................................................. 313
Example of Sequential Mode Setting Procedure ..................................................... 314
Operation in Idle Mode ........................................................................................... 315
Example of Idle Mode Setting Procedure................................................................ 316
Operation in Repeat mode ....................................................................................... 318
Example of Repeat Mode Setting Procedure........................................................... 319
Operation in Single Address Mode (When Sequential Mode Is Specified) ............ 321
(When Sequential Mode Is Specified)..................................................................... 322
Rev.7.00 Mar. 18, 2009 page xlvii of lxvi
REJ09B0109-0700