DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 1197

IC H8S/2378 MCU FLASH 144-LQFP

DF2378BVFQ35V

Manufacturer Part Number
DF2378BVFQ35V
Description
IC H8S/2378 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2378BVFQ35V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
XORC
#xx:8,CCR
XORC
#xx:8,EXR
Reset
exception
handling
Interrupt
exception
handling
Notes: 1. EAs is the ER5 value and EAd the ER6 value. 1 is added to each of them after
Instruction
Advanced
Advanced
2. Repeated two times when two registers are stored/retrieved, three times when three
3. Start address on returning.
4. Start address of program.
5. Prefetch address that is obtained by adding 2 to the saved PC.
6. Start address of interrupt handling routine.
7. Registers ER0, ER1, ER4, and ER5 are used for a TAS instruction.
8. Registers ER0 to ER6 are used for an STM/LDM instruction.
execution.
n is the initial value of R4L or R4, and the processing is not executed when n = 0.
registers are stored/retrieved, and four times when four registers are stored/retrieved.
Reading is not performed on returning from sleep mode or software standby mode, and
this is regarded as internal operation.
R:W
NEXT
R:W 2nd R:W
R:W:M
VEC
R:W *
1
5
NEXT
R:W
VEC+2
1 state of
internal
operation
2
1 state of
internal
operation
W:W
Stack (L)
3
R:W *
W:W
Stack (H)
4
4
W:W
Stack
(EXR)
Rev.7.00 Mar. 18, 2009 page 1129 of 1136
5
R:W:M
VEC
6
R:W
VEC+2
7
REJ09B0109-0700
1 state of
internal
operation
8
Appendix
R:W *
9
6

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