DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 1176

IC H8S/2378 MCU FLASH 144-LQFP

DF2378BVFQ35V

Manufacturer Part Number
DF2378BVFQ35V
Description
IC H8S/2378 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2378BVFQ35V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Appendix
D.
Table D.1 shows the execution state of each instruction in this LSI.
[Explanation of Table Contents:]
[Legend:]
R:B
R:W
W:B
W:W
:M
2nd
3rd
4th
5th
NEXT
EA
VEC
Figure D.1 shows the timing of the address bus, RD, HWR, and LWR during execution of the
sample instruction above (example in "Explanation of Table Contents") with an 8-bit bus, 3-state
access, and no wait.
Rev.7.00 Mar. 18, 2009 page 1108 of 1136
REJ09B0109-0700
Instruction
Bus State during Execution of Instructions
R:W 2nd
1
Reading in bytes
Reading in words
Writing in bytes
Writing in words
Bus mastership cannot be handed over immediately after this cycle
Address of second word (3rd and 4th bytes)
Address of third word (5th and 6th bytes)
Address of fourth word (7th and 8th bytes)
Address of fifth word (9th and 10th bytes)
Start address of instruction immediately following the instruction being executed
Effective address
Vector address
1 state of inter-
nal operation
2
R:W EA
3
4
Order of execution
End of instruction
Read the effective address in words.
Read/write is not performed.
Read the second word of the instruction that is being executed in words.
5
6
7
8

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