DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 323
![IC H8S/2378 MCU FLASH 144-LQFP](/photos/12/29/122922/df2378bvfq35v_sml.jpg)
DF2378BVFQ35V
Manufacturer Part Number
DF2378BVFQ35V
Description
IC H8S/2378 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2378BVFQ35V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space
Access: In a continuous synchronous DRAM space access following a normal space access, the
settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of
consecutive reads in different areas, for example, if the second read is a full access to continuous
synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case
is shown in figure 6.72.
Note: In the H8S/2378 Group, the synchronous DRAM interface is not supported.
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML
differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures
Figure 6.72 Example of Synchronous DRAM Full Access after External Read
Precharge-sel
DQMU, DQML
Address bus
Data bus
CKE
CAS
RAS
WE
RD
φ
External space read
T
1
NOP
T
(CAS Latency 2)
2
T
3
PALL ACTV
Column
address
T
Synchronous DRAM space read
p
Rev.7.00 Mar. 18, 2009 page 255 of 1136
address
address
Row
Row
T
r
READ
T
c1
Column address
Section 6 Bus Controller (BSC)
T
cl
NOP
T
c2
REJ09B0109-0700
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