DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 960

• Manufacturer Part Number: DF2378BVFQ35V
• Description: IC H8S/2378 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 21 Flash Memory (0.18-μm F-ZTAT Version)
(1)
When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communica-
tion data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format
is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the
host by means of the measured low period and transmits the bit adjustment end sign (1 byte of
H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received
normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot
mode is initiated again (reset) and the operation described above must be executed. The bit rate
between the host and this LSI is not matched by the bit rate of transmission by the host and system
clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be
set to 9,600 bps or 19,200 bps.
The system clock frequency, which can automatically adjust the transfer bit rate of the host and
the bit rate of this LSI, is shown in table 21.6. Boot mode must be initiated in the range of this
system clock.
Rev.7.00 Mar. 18, 2009 page 892 of 1136
REJ09B0109-0700
SCI Interface Setting by Host
tool and program
programming
Boot
Host
data
Start
bit
Figure 21.7 Automatic-Bit-Rate Adjustment Operation of SCI
D0
Figure 21.6 System Configuration in Boot Mode
Measure low period (9 bits) (data is H'00)
Control command, program data
D1
Reply response
D2
D3
D4
analysis execution
Control command,
software (on-chip)
RxD1
TxD1
D5
On-chip SCI1
D6
This LSI
D7
On-chip RAM
High period of
at least 1 bit
Stop bit
memory
Flash