DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 345
![IC H8S/2378 MCU FLASH 144-LQFP](/photos/12/29/122922/df2378bvfq35v_sml.jpg)
DF2378BVFQ35V
Manufacturer Part Number
DF2378BVFQ35V
Description
IC H8S/2378 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2378BVFQ35V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.14
6.14.1
In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with
the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR =
H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered
in which the clock is also stopped for the bus controller and I/O ports. In this state, the external
bus release function is halted. To use the external bus release function in sleep mode, the ACSE
bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in all-
module-clocks-stopped mode is executed in the external bus released state, the transition to all-
module-clocks-stopped mode is deferred and performed until after the bus is recovered.
6.14.2
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode,
indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.
6.14.3
CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the
BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR
refresh/auto refresh request is issued.
Note: The auto refresh control is not supported by the H8S/2378 Group.
Usage Notes
External Bus Release Function and All-Module-Clocks-Stopped Mode
External Bus Release Function and Software Standby
External Bus Release Function and CBR Refreshing/Auto Refreshing
Rev.7.00 Mar. 18, 2009 page 277 of 1136
Section 6 Bus Controller (BSC)
REJ09B0109-0700
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