DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 668

• Manufacturer Part Number: DF2378BVFQ35V
• Description: IC H8S/2378 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 16-Bit Timer Pulse Unit (TPU)
Example of PWM Mode Setting Procedure: Figure 11.20 shows an example of the PWM mode
setting procedure.
Examples of PWM Mode Operation: Figure 11.21 shows an example of PWM mode 1
operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as
the duty cycle.
Rev.7.00 Mar. 18, 2009 page 600 of 1136
REJ09B0109-0700
Select counter clearing source
Select waveform output level
Select counter clock
Set PWM mode
<PWM mode>
PWM mode
Start count
Set TGR
Figure 11.20 Example of PWM Mode Setting Procedure
[1]
[2]
[3]
[4]
[5]
[6]
[1] Select the counter clock with bits TPSC2 to
[2] Use bits CCLR2 to CCLR0 in TCR to select the
[3] Use TIOR to designate the TGR as an output
[4] Set the cycle in the TGR selected in [2], and
[5] Select the PWM mode with bits MD3 to MD0 in
[6] Set the CST bit in TSTR to 1 to start the count
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
TGR to be used as the TCNT clearing source.
compare register, and select the initial value and
output value.
set the duty in the other TGRs.
TMDR.
operation.