DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 286

• Manufacturer Part Number: DF2378BVFQ35V
• Description: IC H8S/2378 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.7.3
If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous
DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space;
if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space.
In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be
connected directly.
In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is
enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of
the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.
6.7.4
Table 6.9 shows pins used for the synchronous DRAM interface and their functions. To enable the
synchronous DRAM interface, fix the DCTL pin to 1. Do not vary the DCTL pin during operation.
Since the CS2 to CS4 pins are in the input state after a reset, set DDR to 1 when RAS, CAS, and
WE signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR
register to 1 when the CKE signal is output.
Rev.7.00 Mar. 18, 2009 page 218 of 1136
REJ09B0109-0700
Data Bus
Pins Used for Synchronous DRAM Interface