DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 602
![IC H8S/2378 MCU FLASH 144-LQFP](/photos/12/29/122922/df2378bvfq35v_sml.jpg)
DF2378BVFQ35V
Manufacturer Part Number
DF2378BVFQ35V
Description
IC H8S/2378 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2378BVFQ35V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 602 of 1208
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Section 10 I/O Ports
• PF1/UCAS/IRQ14/DQMU *
Notes: 1. IRQ14 interrupt input when bit ITS14 in ITSR is cleared to 0.
• PF0/WAIT
Rev.7.00 Mar. 18, 2009 page 534 of 1136
REJ09B0109-0700
Operating
mode
EXPE
Areas
2 to 5
PF1DDR
Pin function
Operating
mode
EXPE
WAITE
PF0DDR
Pin function PF0 input
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR.
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
WAITE in BCR, and bit PF0DDR.
2. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
(DQMU) *
Any of
areas 2
to 5 is
DRAM/
synchro-
nous
DRAM *
space
UCAS/
output
⎯
0
2
0
2
PF1 input
Areas 2 to 5 are all
normal space
output
1, 2, 4
1, 2, 4
PF0
⎯
1
⎯
0
2
WAIT
input
output
⎯
PF1
1
1
PF1 input
input
PF0
IRQ14 interrupt *
0
0
⎯
0
⎯
0
output
PF0
1
output
PF1
1
1
PF0 input PF0 output WAIT input
(DQMU) *
Any of
areas 2
to 5 is
DRAM/
synchro-
nous
DRAM *
space
UCAS/
output
0
⎯
7
7
0
2
2
PF1 input
Areas 2 to 5 are all
normal space
1
1
1
0
output
PF1
⎯
1
1
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