HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 283

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

These instructions enable two single-precision (2 × 32-bit) data items to be transferred; that is, the
transfer performance of these instructions is doubled.
• FSCHG
Programming Note:
When FPSCR.SZ = 1 and big-endian mode is used, FMOV can be used for a double-precision
floating-point load or store. In little-endian mode, a double-precision floating-point load or store
requires execution of two 32-bit data size operations with FPSCR.SZ = 0.
6.7
6.7.1
When using the Round to Nearest rounding mode, the underflow flag may not be set in cases
defined as underflow by the IEEE754 standard.
Under the IEEE754 standard, when the Round to Nearest rounding mode is used and infinite-
precision operation result x is (i) or (ii) (single-precision) or (iii) or (iv) (double-precision), there
are cases where “the result after rounding is a normalized number, but an underflow results.”
In such cases where “the result after rounding is a normalized number, but an underflow results,”
the FPU does not set the underflow flag to 1. In these cases the operation result, the value written
to FRn, is correct. Also, if an FPU exception occurs, the underflow flag is not set to 1 but the
inexact flag is set to 1 in such cases. Generation of FPU exceptions can be enabled by setting the
enable field to 1.
(i) H'007FFFFF < x < H'00800000
(ii) H'807FFFFF > x > H'80800000
(iii) H'000FFFFF FFFFFFFF < x < H'00100000 00000000
(iv) H'800FFFFF FFFFFFFF > x > H'80100000 00000000
Examples
• Single-precision
This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use
and non-use of pair single-precision data transfer.
When FPSCR.RM = 00 (Round to Nearest) and FPSCR.PR = 0 (single-precision), and the
FMUL instruction (H'00FFF000 * H'3F000800) is executed.
Usage Notes
Rounding Mode and Underflow Flag
Rev.7.00 Oct. 10, 2008 Page 197 of 1074
Section 6 Floating-Point Unit (FPU)
REJ09B0366-0700