HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 644

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Bit 19—DREQ Select (DS): Specifies either low level detection or falling edge detection as the
sampling method for the DREQ pin used in external request mode.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0–CHCR3.
Bit 19: DS
0
1
Notes: Level detection burst mode when TM = 1 and DS = 0
Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external
device of the acceptance of DREQ) is an active-high or active-low output.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is
invalid.
Bit 18: RL
0
1
Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the
data read cycle or write cycle. In single address mode, DACK is always output regardless of the
setting of this bit.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is
valid for CHCR1 to CHCR3 in the SH7750. In the SH7750S, this bit is valid for CHCR0 to
CHCR3. (DDT mode: TDACK)
Bit 17: AM
0
1
Rev.7.00 Oct. 10, 2008 Page 558 of 1074
REJ09B0366-0700
Edge detection burst mode when TM = 1 and DS = 1
Description
Low level detection
Falling edge detection
Description
DRAK is an active-high output
DRAK is an active-low output
Description
DACK is output in read cycle
DACK is output in write cycle
(Initial value)
(Initial value)
(Initial value)