HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 65

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 1 Overview
Figure 1.1
Figure 1.2
Figure 1.3
Figure 1.4
Figure 1.5
Section 2 Programming Model
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Section 3 Memory Management Unit (MMU)
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3.8
Figure 3.9
Figure 3.10 Flowchart of Memory Access Using UTLB........................................................... 91
Figure 3.11 Flowchart of Memory Access Using ITLB ............................................................ 92
Figure 3.12 Operation of LDTLB Instruction............................................................................ 94
Figure 3.13 Memory-Mapped ITLB Address Array.................................................................. 103
Figure 3.14 Memory-Mapped ITLB Data Array 1 .................................................................... 104
Figure 3.15 Memory-Mapped ITLB Data Array 2 .................................................................... 105
Figure 3.16 Memory-Mapped UTLB Address Array ................................................................ 107
Figure 3.17 Memory-Mapped UTLB Data Array 1................................................................... 108
Figure 3.18 Memory-Mapped UTLB Data Array 2................................................................... 109
Section 4 Caches
Figure 4.1
Block Diagram of SH7750/SH7750S/SH7750R Group Functions ........................
Pin Arrangement (256-Pin BGA)........................................................................... 10
Pin Arrangement (208-Pin QFP) ............................................................................ 11
Pin Arrangement (264-Pin CSP) ............................................................................ 12
Pin Arrangement (292-Pin BGA)........................................................................... 13
Data Formats .......................................................................................................... 53
CPU Register Configuration in Each Processor Mode........................................... 56
General Registers ................................................................................................... 58
Floating-Point Registers ......................................................................................... 61
Data Formats In Memory ....................................................................................... 67
Processor State Transitions .................................................................................... 68
Role of the MMU ................................................................................................... 73
MMU-Related Registers......................................................................................... 75
Physical Address Space (MMUCR.AT = 0) .......................................................... 79
P4 Area................................................................................................................... 81
External Memory Space ......................................................................................... 82
Virtual Address Space (MMUCR.AT = 1)............................................................. 83
UTLB Configuration .............................................................................................. 86
Relationship between Page Size and Address Format............................................ 87
ITLB Configuration................................................................................................ 90
Cache and Store Queue Control Registers ............................................................. 114
Figures
Rev.7.00 Oct. 10, 2008 Page lxiii of lxxxiv
REJ09B0366-0700
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