HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 656

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Section 14 Direct Memory Access Controller (DMAC)
Table 14.4 Selecting External Request Mode with RS Bits
RS3
0
• External Request Acceptance Conditions
Rev.7.00 Oct. 10, 2008 Page 570 of 1074
REJ09B0366-0700
1. When at least one of DMAOR.DME and CHCR.DE is 0, and DMAOR.NMIF,
2. When DMA transfer is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0,
3. An external request (DREQ) will be ignored if input when CHCR.TE = 1, DMAOR.NMIF
4. A previously input external request will be canceled by the occurrence of an NMI interrupt
DMAOR.AE, and CHCR.TE are all 0, if an external request (DREQ: edge-detected) is
input it will be held inside the DMAC until DMA transfer is either executed or canceled.
Since DMA transfer is not enabled in this case (DME = 0 or DE = 0), DMA transfer is not
initiated. DMA transfer is started after it is enabled (DME = 1, DE = 1, DMAOR.NMIF =
0, DMAOR.AE = 0, CHCR.TE = 0).
CHCR.TE = 0), if an external request (DREQ) is input, DMA transfer is started.
= 1, or DMAOR.AE = 1, or during a power-on reset or manual reset, in deep sleep mode or
standby mode, or while the DMAC is in the module standby state.
(DMAOR.NMIF = 1) or address error (DMAOR.AE = 1), or by a power-on reset or
manual reset.
In the SH7750S, it is possible to cancel a previously input external request (DREQ). With
DMAOR.COD set to 1, clear CHCRn.DS to 0 and then drive the DREQ pin high.
On the SH7750R, it is possible to cancel an external request that has been accepted by
external request (DREQ) edge detection by first negating DREQ and then clearing
CHCR.DS from 1 to 0. Afterwards CHCR.DS should be reset to 1 and DREQ asserted.
(The SH7750R has no DMAOR.COD bit, but it is possible to cancel an external request
that has been accepted by external request (DREQ) edge detection, as is the case when the
DMAOR.COD bit of the SH7750S is set to 1.)
RS2
0
RS1
0
1
RS0
0
0
1
Address Mode
Dual address
mode
Single address
mode
Single address
mode
Transfer Source
External memory
or memory-mapped
external device, or
external device with
DACK
External memory
or memory-mapped
external device
External device with
DACK
Transfer Destination
External memory
or memory-mapped
external device, or
external device with
DACK
External device
with DACK
External memory
or memory-mapped
external device

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