HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 638

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
14.2
14.2.1
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. These registers have a counter feedback function,
and during a DMA transfer they indicate the next source address. In single address mode, the SAR
value is ignored when an external device with DACK has been specified as the transfer source.
Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64-
bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will
be detected and the DMAC will halt.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode and deep sleep mode.
When transfer is performed from memory to an external device with DACK in DDT mode, DTR
format [31:0] is set in SAR0 [31:0]. For details, see Data Transfer Request Format in section
14.5.2, Pin in DDT Mode.
Rev.7.00 Oct. 10, 2008 Page 552 of 1074
REJ09B0366-0700
Initial value:
Initial value:
Register Descriptions (SH7750, SH7750S)
DMA Source Address Registers 0–3 (SAR0–SAR3)
R/W:
R/W:
Bit:
Bit:
R/W
R/W
31
23
—
—
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R/W
30
—
R/W
29
—
R/W
28
—
R/W
27
—
R/W
26
—
R/W
25
—
R/W
R/W
24
—
—
0