HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 353
HD6417750RF200DV
Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750RF200DV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
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9.2.5
Clock-stop register 00 (CLKSTP00) controls the operation clock for peripheral modules. To
resume supply of the clock signal, write a 1 to the corresponding bit in the CLKSTPCLR00
register. Writing a 0 to the CLKSTP00 register does not affect the register's value. The
CLKSTP00 register is a 32-bit register that can be read from or written to. It is initialized to
H'0000 0000 by a power-on reset, but not by a manual reset or when the device enters standby
mode.
Bits 31 to 2—Reserved: Any data written to these bits should always be 0. These bits are always
read as 0.
Bit 1—Clock stop 1 (CSTP1): This bit specifies stopping of the peripheral clock supply to
channels 3 and 4 of the timer unit (TMU).
Bit 1: CSTP1
0
1
Bit 0⎯Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt
controller (INTC). If this bit is set, INTC does not detect interrupts on the TMU's channels 3 and
4.
Bit 0: CSTP0
0
1
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Clock-Stop Register 00 (CLKSTP00) (SH7750R Only)
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
Description
Peripheral clock is supplied to TMU channels 3 and 4
Peripheral clock supply to TMU channels 3 and 4 is stopped
Description
INTC detects interrupts on channels 3 and 4 of the TMU
INTC does not detect interrupts on channels 3 and 4 of the TMU
29
13
—
—
R
R
0
0
28
12
—
—
R
R
0
0
27
—
11
—
R
R
0
0
26
10
—
—
R
R
0
0
25
—
—
R
R
0
9
0
24
—
—
R
R
0
8
0
Rev.7.00 Oct. 10, 2008 Page 267 of 1074
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
Section 9 Power-Down Modes
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
REJ09B0366-0700
(Initial value)
(Initial value)
18
—
—
R
R
0
2
0
CSTP1 CSTP0
R/W R/W
17
—
R
0
1
0
16
—
R
0
0
0
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