HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 553

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2–
AMX0 in MCR. Table 13.16 shows the relationship between the address multiplex specification
bits and the bits output at the address pins. See Appendix F, Synchronous DRAM Address
Multiplexing Tables.
Address pin output at A25–A18, A1, and A0 are undefined.
When A0, the LSB of the synchronous DRAM address, is connected to this LSI, with a 32-bit bus
width it makes a longword address specification. Connection should therefore be made in this
order: connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect pin A1 to pin
A3.
With a 64-bit bus width, the LSB makes a quadword address specification. Connection should
therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A3 of this LSI,
then connect pin A1 to pin A4.
Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)
SH7750, SH7750S, SH7750R
D31–D16
D15–D0
A11–A2
RD/WR
DQM3
DQM2
DQM1
DQM0
CASS
CKIO
CKE
RAS
CS3
Rev.7.00 Oct. 10, 2008 Page 467 of 1074
Section 13 Bus State Controller (BSC)
512K × 16-bit × 2-bank
synchronous DRAM
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
REJ09B0366-0700

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