HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 313

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 7.12 Floating-Point Graphics Acceleration Instructions
Instruction
FMOV
FMOV
FMOV
FMOV
FMOV
FMOV
FMOV
FMOV
FMOV
FIPR
FTRV
FRCHG
FSCHG
7.4
7.4.1
• Incorrect data may be written to the cache when a TRAPA instruction or undefined instruction
• The ITLB hit judgment may be incorrect when a TRAPA instruction or undefined instruction
• Incorrect data may be written to an FPU-related register or to the MACH or MACL register
Conditions Under which Problem Occurs
1. Incorrect data may be written to the instruction cache when the following three conditions
code H'FFFD is executed.
code H'FFFD is executed, causing a multi-hit exception to occur after re-registration.
when a TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is
executed.
occur at the same time.
a. The instruction cache is enabled (CCR.ICE = 1).
DRm,XDn
XDm,DRn
XDm,XDn
@Rm,XDn
@Rm+,XDn
@(R0,Rm),XDn
XDm,@Rn
XDm,@-Rn
XDm,@(R0,Rn)
FVm,FVn
XMTRX,FVn
Usage Notes
Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction
(H'FFFD)
Operation
DRm → XDn
XDm → DRn
XDm → XDn
(Rm) → XDn
(Rm) → XDn, Rm + 8 → Rm
(R0 + Rm) → XDn
XDm → (Rn)
Rn – 8 → Rn, XDm → (Rn)
XDm → (R0+Rn)
inner_product [FVm, FVn] →
FR[n+3]
transform_vector [XMTRX, FVn]
→ FVn
~FPSCR.FR → FPSCR.FR
~FPSCR.SZ → FPSCR.SZ
Instruction Code
1111nnn1mmm01100 —
1111nnn0mmm11100 —
1111nnn1mmm11100 —
1111nnn1mmmm1000 —
1111nnn1mmmm1001 —
1111nnn1mmmm0110 —
1111nnnnmmm11010 —
1111nnnnmmm11011 —
1111nnnnmmm10111 —
1111nnmm11101101 —
1111nn0111111101 —
1111101111111101 —
1111001111111101 —
Rev.7.00 Oct. 10, 2008 Page 227 of 1074
Section 7 Instruction Set
Privileged
REJ09B0366-0700
T Bit
—
—
—
—
—
—
—
—
—
—
—
—
—