HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 637

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Chan-
nel
1
2
3
Com-
mon
Notes: Longword access should be used for all control registers. If a different access width is
Name
DMA source
address register 1
DMA destination
address register 1
DMA transfer
count register 1
DMA channel
control register 1
DMA source
address register 2
DMA destination
address register 2
DMA transfer
count register 2
DMA channel
control register 2
DMA source
address register 3
DMA destination
address register 3
DMA transfer
count register 3
DMA channel
control register 3
DMA operation
register
used, reads will return all 0s and writes will not be possible.
1. Bit 1 of CHCR0–CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after
2. In the SH7750, writes from the CPU are masked in DDT mode, while writes from
being read as 1, to clear the flags.
external I/O devices using the DTR format are possible. In the SH7750S, writes from
the CPU and writes from external I/O devices using the DTR format are possible in DDT
mode.
Abbre-
viation
SAR1
DAR1
DMATCR1 R/W
CHCR1
SAR2
DAR2
DMATCR2 R/W
CHCR2
SAR3
DAR3
DMATCR3 R/W
CHCR3
DMAOR
Read/
Write
R/W
R/W
R/W *
R/W
R/W
R/W *
R/W
R/W
R/W *
R/W *
Section 14 Direct Memory Access Controller (DMAC)
1
1
1
1
Initial Value P4 Address
Undefined
Undefined
Undefined
H'00000000 H'FFA0001C H'1FA0001C 32
Undefined
Undefined
Undefined
H'00000000 H'FFA0002C H'1FA0002C 32
Undefined
Undefined
Undefined
H'00000000 H'FFA0003C H'1FA0003C 32
H'00000000 H'FFA00040 H'1FA00040 32
Rev.7.00 Oct. 10, 2008 Page 551 of 1074
H'FFA00010 H'1FA00010 32
H'FFA00014 H'1FA00014 32
H'FFA00018 H'1FA00018 32
H'FFA00020 H'1FA00020 32
H'FFA00024 H'1FA00024 32
H'FFA00028 H'1FA00028 32
H'FFA00030 H'1FA00030 32
H'FFA00034 H'1FA00034 32
H'FFA00038 H'1FA00038 32
Area 7
Address
REJ09B0366-0700
Access
Size

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