HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 636

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Table 14.2 DMAC Pins in DDT Mode
Pin Name
Data bus request
Data bus available
Transfer request signal
DMAC strobe
Channel number
notification
14.1.4
Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers
are allocated to each channel, and an additional control register is shared by all four channels.
Table 14.3 DMAC Registers
Chan-
nel
0
Rev.7.00 Oct. 10, 2008 Page 550 of 1074
REJ09B0366-0700
Name
DMA source
address register 0
DMA destination
address register 0
DMA transfer
count register 0
DMA channel
control register 0
Register Configuration (SH7750, SH7750S)
Abbreviation
DBREQ
(DREQ0)
BAVL
(DRAK0)
TR
(DREQ1)
TDACK
(DACK0)
ID [1:0]
(DRAK1, DACK1)
Abbre-
viation
SAR0
DAR0
DMATCR0 R/W *
CHCR0
Read/
Write
R/W *
R/W *
R/W *
2
2
2
1
*
Input
Output
Input
Output
Output
I/O
2
Initial Value P4 Address
Undefined
Undefined
Undefined
H'00000000 H'FFA0000C H'1FA0000C 32
Function
Data bus release request from external
device for DTR format input
Data bus release notification
Data bus can be used 2 cycles after
BAVL is asserted
If asserted 2 cycles after BAVL
assertion, DTR format is sent
Only TR asserted: DMA request
DBREQ and TR asserted
simultaneously: Direct request to
channel 2
Reply strobe signal for external device
from DMAC
Notification of channel number to
external device at same time as TDACK
output
(ID [1] = DRAK1, ID [0] = DACK1)
H'FFA00000 H'1FA00000 32
H'FFA00004 H'1FA00004 32
H'FFA00008 H'1FA00008 32
Area 7
Address
Access
Size