HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 348

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 Power-Down Modes
9.2
9.2.1
The standby control register (STBCR) is an 8-bit readable/writable register that specifies the
power-down mode status. It is initialized to H'00 by a power-on reset via the RESET pin or due to
watchdog timer overflow.
Bit 7—Standby (STBY): Specifies a transition to standby mode.
Bit 7: STBY
0
1
Bit 6—Peripheral Module Pin High Impedance Control (PHZ): Controls the state of
peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module
related pins go to the high-impedance state in standby mode.
For the relevant pins, see section 9.2.2, Peripheral Module Pin High Impedance Control.
Bit 6: PHZ
0
1
Bit 5—Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module
related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral
module related pins in the input or high-impedance state.
For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control.
Bit 5: PPU
0
1
Rev.7.00 Oct. 10, 2008 Page 262 of 1074
REJ09B0366-0700
Initial value:
Register Descriptions
Standby Control Register (STBCR)
R/W:
Bit:
STBY
Description
Transition to sleep mode on execution of SLEEP instruction
Transition to standby mode on execution of SLEEP instruction
Description
Peripheral module related pins are in normal state
Peripheral module related pins go to high-impedance state
Description
Peripheral module related pin pull-up resistors are on
Peripheral module related pin pull-up resistors are off
R/W
7
0
PHZ
R/W
6
0
PPU
R/W
5
0
MSTP4
R/W
4
0
MSTP3
R/W
3
0
MSTP2
R/W
2
0
MSTP1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
MSTP0
R/W
0
0