HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 944

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Section 20 User Break Controller (UBC)
Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify
whether an instruction access cycle or an operand access cycle is used as the bus cycle in the
channel A break conditions.
Bit 5: IDA1
0
1
Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits specify whether a read cycle or
write cycle is used as the bus cycle in the channel A break conditions.
Bit 3: RWA1
0
1
Bits 6, 1, and 0—Operand Size Select A (SZA2–SZA0): These bits select the operand size of
the bus cycle used as a channel A break condition.
Bit 6: SZA2
0
1
Legend: *: Don't care
Rev.7.00 Oct. 10, 2008 Page 858 of 1074
REJ09B0366-0700
Bit 1: SZA1
0
1
0
1
Bit 4: IDA0
0
1
0
1
Bit 2: RWA0
0
1
0
1
Bit 0: SZA0
0
1
0
1
0
1
*
Description
Condition comparison is not performed
Instruction access cycle is used as break condition
Operand access cycle is used as break condition
Instruction access cycle or operand access cycle is used as
break condition
Description
Condition comparison is not performed
Read cycle is used as break condition
Write cycle is used as break condition
Read cycle or write cycle is used as break condition
Description
Operand size is not included in break conditions
Byte access is used as break condition
Word access is used as break condition
Longword access is used as break condition
Quadword access is used as break condition
Reserved (cannot be set)
Reserved (cannot be set)
(Initial value)
(Initial value)
(Initial value)

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