UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 119

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(5) Oscillation stabilization time counter status register (OSTC)
This is the status register of the high-speed system clock oscillation stabilization time counter. If the internal
oscillation clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be
checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction,
MSTOP = 1, and MCC = 1 clear OSTC to 00H.
Address: FFA3H
Symbol
OSTC
Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Remark f
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
MOST11
7
0
1
1
1
1
1
After reset: 00H
2. If the STOP mode is entered and then released while the internal oscillation is
3. The wait time when STOP mode is released does not include the time after STOP
XP
: High-speed system clock oscillation frequency
MOST13
remain 1.
being used as the CPU clock, set the oscillation stabilization time as follows.
The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
6
0
0
1
1
1
1
X1 pin voltage
waveform
Desired OSTC oscillation stabilization time
set by OSTS
R
CHAPTER 5 CLOCK GENERATOR
MOST14
User’s Manual U16899EJ3V0UD
5
0
0
0
1
1
1
STOP mode release
MOST11
MOST15
4
0
0
0
1
1
a
MOST13
MOST16
3
0
0
0
0
1
2
2
2
2
2
MOST14
11
13
14
15
16
Oscillation stabilization time status
/f
/f
/f
/f
/f
XP
XP
XP
XP
XP
2
min.
min.
min.
min.
min.
Oscillation stabilization time
f
204.8 s min. 128 s min.
819.2 s min. 512 s min.
1.64 ms min. 1.02 ms min.
3.27 ms min. 2.04 ms min.
6.55 ms min. 4.09 ms min.
XP
MOST15
= 10 MHz f
1
XP
MOST16
= 16 MHz
0
117