UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 182

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(8) Timer operation
(9) Capture operation
(10) Compare operation
(11) Edge detection
180
<2> The sampling clock used to remove noise differs when the TI00n pin valid edge is used as the count clock
<1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit timer capture/compare
<2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI00n/TI01n pins
<3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
<1> If the TI00n pin valid edge is specified as the count clock, a capture operation by the capture register
<2> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles
<3> The capture operation is performed at the falling edge of the count clock. An interrupt request input
A capture operation may not be performed for CR00n/CR01n set in compare mode even if a capture trigger has
been input.
<1> If the TI00n or TI01n pin is high level immediately after system reset and the rising edge or both the rising
register 01n (CR01n).
are not acknowledged.
clear & start occurs at the TI00n valid edge. In the mode in which clear & start occurs on a match between
the TM0n register and CR00n register, one-shot pulse output is not possible because an overflow does not
occur.
specified as the trigger for the TI00n pin is not possible.
of the count clock selected by prescaler mode register 0n (PRM0n).
(INTTM00n/INTTM01n), however, is generated at the rise of the next count clock.
and falling edges are specified as the valid edge of the TI00n or TI01n pin to enable the 16-bit timer counter
0n (TM0n) operation, a rising edge is detected immediately after the operation is enabled. Be careful
therefore when pulling up the TI00n or TI01n pin. However, if the TI00n or TI01n pin is high level when re-
enabling operation after the operation has been stopped, the rising edge is not detected.
and when it is used as a capture trigger. In the former case, the count clock is f
count clock is selected by prescaler mode register 0n (PRM0n). The capture operation is started only after
a valid edge is detected twice by sampling, thus eliminating noise with a short pulse width.
Remark n = 0:
n = 0, 1: PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
PD78F0132H
User’s Manual U16899EJ3V0UD
X
, and in the latter case the