UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 219

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
8-bit timer counter Hn
<1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
<5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output
<6> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive.
(TOLEVn = 0)
Count clock
clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0).
to the count clock.
is cleared, the TOHn output becomes active, and the INTTMHn signal is output.
values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to
the CMP1n register and the CMP1n register value is changed (<2>’).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
Remark n = 0, 1
INTTMHn
TMHEn
CMP0n
CMP1n
TOHn
(e) Operation by changing CMP1n (CMP1n = 01H
00H 01H 02H
<1>
Figure 8-12. Operation Timing in PWM Output Mode (4/4)
01H
CHAPTER 8 8-BIT TIMERS H0 AND H1
<2>
A5H 00H 01H 02H 03H
User’s Manual U16899EJ3V0UD
<3>
01H (03H)
<2>'
<4>
A5H
03H
A5H 00H 01H 02H 03H
03H, CMP0n = A5H)
<5>
A5H 00H
<6>
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