UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 314

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
312
1. Stop bit length: 1
2. Stop bit length: 2
(c) Normal transmission
The T
register 6 (ASIM6) is set to 1.
Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity
bit, and stop bit are automatically appended to the data.
When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,
the data is sequentially output from TXS6 to the T
stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated.
Transmission is stopped until the data to be transmitted next is written to TXB6.
Figure 14-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt
occurs as soon as the last stop bit has been output.
T
T
X
X
D6 (output)
D6 (output)
X
INTST6
INTST6
D6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode
Figure 14-15. Normal Transmission Completion Interrupt Request Timing
Start
Start
CHAPTER 14 SERIAL INTERFACE UART6
D0
D0
If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled.
User’s Manual U16899EJ3V0UD
D1
D1
D2
D2
X
D6 pin. When transmission is completed, the parity and
D6
D6
D7
D7
Parity
Parity
Stop
Stop

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