UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 401

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

21.1 Functions of Clock Monitor
internal reset signal when the high-speed system clock is stopped.
to 1. For details of RESF, see CHAPTER 20 RESET FUNCTION.
21.2 Configuration of Clock Monitor
Control register
The clock monitor samples the high-speed system clock using the on-chip internal oscillator, and generates an
When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set
The clock monitor automatically stops under the following conditions.
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
The clock monitor includes the following hardware.
Remark MCC:
Reset is released and during the oscillation stabilization time
In STOP mode and during the oscillation stabilization time
When the high-speed system clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation
stabilization time
When the internal oscillation clock is stopped
Item
oscillation stabilization status
MCC:
MSTOP: Bit 7 of the main OSC control register (MOC)
OSTC:
High-speed system clock
High-speed system clock
oscillation control signal
Clock monitor mode register (CLM)
Bit 7 of the processor clock control register (PCC)
Bit 7 of the processor clock control register (PCC)
Oscillation stabilization time counter status register (OSTC)
(OSTC overflow)
(MCC, MSTOP)
Figure 21-1. Block Diagram of Clock Monitor
Table 21-1. Configuration of Clock Monitor
Internal oscillation clock
CHAPTER 21 CLOCK MONITOR
Operation mode
User’s Manual U16899EJ3V0UD
Internal bus
system clock
controller
CLME
High-speed
Clock monitor
mode register (CLM)
Configuration
High-speed system
clock oscillation
monitor circuit
Internal reset
signal
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