UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 562

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

560
ROM
correction
Flash
memory
Function
CORAD0,
CORAD1:
Correction
address
registers 0 and
1
Cautions for
ROM correction
IMS: Internal
memory size
switching
register
IXS: Internal
expansion RAM
size switching
register
UART6
FLPMC: Flash-
programming
mode control
register
Details of
Function
The ROM correction cannot be emulated by the in-circuit emulator.
Set the CORAD0 and CORAD1 when bit 1 (COREN0) and bit 3 (COREN1) of the
correction control register (CORCN: see Figure 25-3) are 0.
Only addresses where operation codes are stored can be set in CORAD0 and
CORAD1.
Do not set the following addresses to CORAD0 and CORAD1.
Address values set in correction address registers 0 and 1 (CORAD0, CORAD1)
must be addresses where instruction codes are stored.
Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when
the correction enable flag (COREN0, COREN1) is 0 (when the correction branch
is in disabled state). If address is set to CORAD0 or CORAD1 when COREN0 or
COREN1 is 1 (when the correction branch is in enabled state), the correction
branch may start with the different address from the set address value.
Do not set the address value of instruction immediately after the instruction that
sets the correction enable flag (COREN0, COREN1) to 1, to correction address
register 0 or 1 (CORAD0, CORAD1); the correction branch may not start.
Do not set the address value in table area of table reference instruction (CALLT
instruction) (0040H to 007FH), and the address value in vector table area (0000H
to 003FH) to correction address registers 0 and 1 (CORAD0, CORAD1).
Do not set two addresses immediately after the instructions shown below to
correction address registers 0 and 1 (CORAD0, CORAD1). (That is, when the
mapped terminal address of these instructions is N, do not set the address values
of N + 1 and N + 2.)
There are differences in noise immunity and noise radiation between the flash
memory and mask ROM versions. When pre-producing an application set with
the flash memory version and then mass-producing it with the mask ROM
version, be sure to conduct sufficient evaluations for the commercial samples (not
engineering samples) of the mask ROM versions.
The initial value of IMS is CFH. Be sure to set each product to the values shown
in Table 26-2 at initialization. Also, when using the 78K0/KE1+ to evaluate the
program of a mask ROM version of the 78K0/KE1, be sure to set the values
shown in Table 26-2.
The initial value of IXS is 0CH. Be sure to set each product to the values shown
in Table 26-3 at initialization. Also, when using the 78K0/KE1+ to evaluate the
program of a mask ROM version of the 78K0/KE1, be sure to set the values
shown in Table 26-3.
When UART6 is selected, the receive clock is calculated based on the reset
command sent from the dedicated flash programmer after the FLMD0 pulse has
been received.
Be sure to keep FWEDIS at 0 until writing or erasing of the flash memory is
completed.
Make sure that FWEDIS = 1 in the normal mode.
Manipulate FLSPM1 and FLSPM0 after execution branches to the internal RAM.
The address of the flash memory is specified by an address signal from the CPU
when FLSPM1 = 0 or the set value of the firmware written when FLSPM1 = 1. In
the on-board mode, the specifications of FLSPM1 and FLSPM0 are ignored.
Address value in table area of table reference instruction (CALLT instruction):
Address value in vector table area: 0000H to 003FH
0040H to 007FH
APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ3V0UD
Cautions
p. 423
p. 424
p. 432
p. 432
p. 432
p. 432
p. 432
p. 433
p. 434
p. 435
p. 449
p. 453
p. 453
p. 453
p. 424
p. 424
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