UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 177

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
(2) One-shot pulse output with external trigger
Caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is
Remark N < M
A one-shot pulse can be output from the TO0n pin by setting 16-bit timer mode control register 0n (TMC0n),
capture/compare control register 0n (CRC0n), and 16-bit timer output control register 0n (TOC0n) as shown in
Figure 6-38, and by using the valid edge of the TI00n pin as an external trigger.
The valid edge of the TI00n pin is specified by bits 4 and 5 (ES0n0, ES0n1) of prescaler mode register 0n
(PRM0n). The rising, falling, or both the rising and falling edges can be specified.
When the valid edge of the TI00n pin is detected, the 16-bit timer/event counter is cleared and started, and the
output becomes active at the count value set in advance to 16-bit timer capture/compare register 01n (CR01n).
After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register
00n (CR00n)
Note The case where N < M is described here. When N > M, the output becomes active with the CR00n register
Caution Even if the external trigger is generated again while the one-shot pulse is output, it is ignored.
Remark n = 0:
CR01n set value
CR00n set value
TO0n pin output
Count clock
TM0n count
INTTM01n
INTTM00n
and inactive with the CR01n register. Do not set N to M.
OSPT0n
set to the TMC0n3 and TMC0n2 bits.
n = 0, 1: PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD
Figure 6-37. Timing of One-Shot Pulse Output Operation with Software Trigger
Note
.
Set TMC0n to 04H
(TM0n count starts)
0000H
PD78F0132H
M
N
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
0001H
N
User’s Manual U16899EJ3V0UD
N + 1
N
M
0000H
N – 1
M
N
N
M – 1
M
M
N
M + 1 M + 2
175

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