UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 553

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

A/D
converter
Serial
interface
UART0
Function
Register
generating wait
cycle
UART mode
TXS0: Transmit
shift register 0
ASIM0:
Asynchronous
serial interface
operation mode
register 0
ASIS0:
Asynchronous
serial interface
reception error
Details of
Function
Do not read data from the ADCR register and do not write data to the ADM, ADS,
PFM, and PFT registers while the CPU is operating on the subsystem clock and
while high-speed system clock oscillation is stopped.
If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode),
normal operation continues. If clock supply to serial interface UART0 is stopped
(e.g., in the STOP mode), each register stops operating, and holds the value
immediately before clock supply was stopped. The TxD0 pin also holds the value
immediately before clock supply was stopped and outputs it. However, the
operation is not guaranteed after clock supply is resumed. Therefore, reset the
circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception)
to start communication.
TXE0 and RXE0 are synchronized by the base clock (f
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may
not be initialized.
Set transmit data to TXS0 at least two base clocks after setting POWER0 = 1 and
one base clock after setting TXE0 = 1.
Do not write the next transmit data to TXS0 before the transmission completion
interrupt signal (INTST0) is generated.
Set transmit data to TXS0 at least two base clocks after setting POWER0 = 1 and
one base clock after setting TXE0 = 1.
At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear
TXE0 to 0, and then clear POWER0 to 0.
At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation,
clear RXE0 to 0, and then clear POWER0 to 0.
Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0
pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input,
reception is started.
TXE0 and RXE0 are synchronized by the base clock (f
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may
not be initialized.
Set transmit data to TXS0 at least two base clocks after setting POWER0 = 1 and
one base clock after setting TXE0 = 1.
Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0
bits.
Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always
performed with “number of stop bits = 1”, and therefore, is not affected by the set
value of the SL0 bit.
Be sure to set bit 0 to 1.
The operation of the PE0 bit differs depending on the set values of the PS01 and
PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0).
Only the first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer
register 0 (RXB0) but discarded.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ3V0UD
Cautions
XCLK0
XCLK0
) set by BRGC0. To
) set by BRGC0. To
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