UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 476

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

474
Conditional
branch
CPU
control
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
BT
BF
BTCLR
DBNZ
SEL
NOP
EI
DI
HALT
STOP
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
C, $addr16
Saddr, $addr16
RBn
Operands
CHAPTER 28 INSTRUCTION SET
User’s Manual U16899EJ3V0UD
Bytes
3
4
3
3
3
4
4
3
4
3
4
4
3
4
3
2
2
3
2
1
2
2
2
2
Note 1
10
10
10
10
10
8
8
8
8
6
6
8
4
2
6
6
Clocks
Note 2
11
11
11
11
11
11
12
12
12
12
10
9
9
6
6
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
if(saddr.bit) = 1
then reset(saddr.bit)
PC
then reset sfr.bit
PC
then reset A.bit
PC
then reset PSW.bit
PC
then reset (HL).bit
B
PC
C
PC
(saddr)
PC
RBS1, 0
No Operation
IE
IE
Set HALT Mode
Set STOP Mode
B
C 1, then
1(Enable Interrupt)
0(Disable Interrupt)
PC + 3 + jdisp8 if(saddr.bit) = 1
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 3 + jdisp8 if PSW.bit = 1
PC + 3 + jdisp8 if (HL).bit = 1
PC + 4 + jdisp8 if(saddr.bit) = 0
PC + 4 + jdisp8 if sfr.bit = 0
PC + 3 + jdisp8 if A.bit = 0
PC + 4 + jdisp8 if PSW. bit = 0
PC + 3 + jdisp8 if (HL).bit = 0
PC + 4 + jdisp8
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 4 + jdisp8 if PSW.bit = 1
PC + 3 + jdisp8 if (HL).bit = 1
PC + 2 + jdisp8 if B
PC + 2 + jdisp8 if C
PC + 3 + jdisp8 if(saddr)
1, then
(saddr)
n
CPU
) selected by the processor clock
Operation
1, then
0
0
0
Z AC CY
Flag