SC900841JVKR2 Freescale Semiconductor, SC900841JVKR2 Datasheet - Page 137

• Manufacturer Part Number: SC900841JVKR2
• Description: IC POWER MGT 338-MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of SC900841JVKR2

• Applications: PC's, PDA's
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 338-TBGA
• Input Voltage: 2.8 V to 4.4 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STEREO DAC AND ADC PROTOCOL
the I
formats, and can be used in either master or slave mode.
Master mode is selected by setting the STRMASTEN bit. In
master mode, the stereo codec generates the bit clock and
frame sync signals, as long as the STRCLKEN bit is set. The
data is transmitted and received in a two's complement
format, MSB first, and can be clocked on the positive or
negative edge of the bit clock. The active edge of the bit clock
can be selected by the STRBCLINV bit.
sync, which also identifies left vs. right stereo channel words.
In I
Analog Integrated Circuit Device Data
Freescale Semiconductor
The serial interface protocol for the audio data uses either
The interface operates with a long (word-length) frame
2
S mode, the frame sync leads the data MSB by 1 bit clock
2
S standard, Left-Justified or EIAJ Right-justified
MODE 5: Short Frame Sync, 4 Words
FS1
BCL1
RX1
TX1
MODE 6: Long Frame Sync, 4 Words
FS1
BCL1
RX1
TX1
Figure 69. Voice CODEC Serial Interface Timing Diagram Modes 5-6
Hi-
Z
Hi-
Z
Bit n
Bit n
Bit n
Bit n
Slot 0
Slot 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit n
Bit n
Bit n
Bit n
Slot 1
Slot 1
Bit 0
Bit 0
Bit 0
Bit 0
cycle, while in Left-justified mode the frame sync is aligned
with the MSB of the data, and in Right-justified mode the
frame sync is aligned with the LSB of the data. The mode is
selected with the STRMODESEL bits. Note that in all modes,
the left channel word is sent in the first half of the frame and
the right channel word is sent in the second half of the frame.
Supported word lengths are 16 to 32 bits. The word length is
set with the STRWORDLEN[2:0] bits and the bit clock
frequency is set with the STRCLKFRQ[2:0] bits. The frame
sync can also be inverted by setting the STRFSINV bit. The
tri-state enable can be controlled by the STRTSB bit.
Figure
Bit n
Bit n
The timing diagrams for these modes are given in
Bit n
Bit n
Slot 2
70.
Bit 0
Bit 0
Bit 0
Bit 0
Bit n
Bit n
Bit n
Bit n
Slot 3
Slot 3
Bit 0
Bit 0
Bit 0
Bit 0
FUNCTIONAL DEVICE OPERATION
Bit n
Bit n
Bit n
Bit n
Slot 0
Slot 0
AUDIO
900841
137