SC900841JVKR2 Freescale Semiconductor, SC900841JVKR2 Datasheet - Page 56

• Manufacturer Part Number: SC900841JVKR2
• Description: IC POWER MGT 338-MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of SC900841JVKR2

• Applications: PC's, PDA's
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 338-TBGA
• Input Voltage: 2.8 V to 4.4 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

the SET bit in Register B is clear. The SET bit in the “1” state
permits the program to initialize the time and calendar bytes
by stopping an existing update and preventing a new one
from occurring.
the Seconds byte, check for overflow, increment the Minutes
byte when appropriate, and so forth, up through the month
and year bytes. The update cycle also compares each alarm
byte with the corresponding time byte and issues an alarm if
a match is present in all three positions.
are usable by the program. In discussing the two methods, it
is assumed that at random points, user programs are able to
call a subroutine to obtain the time of day.
enabled, an interrupt occurs after every update cycle, which
indicates that over 999 ms are available to read valid time
and date information. Before leaving the interrupt service
routine, the IRQF bit in Register C should be cleared.
in Register A, to determine if the update cycle is in progress.
The UIP bit will pulse once per second. Statistically, the UIP
bit will indicate that time and date information is unavailable
once every 3,640 attempts. After the UIP bit goes high, the
update cycle begins 244.1 μs later. Therefore, if a low is read
on the UIP bit, the user has at least 244.1 μs before the time/
calendar data will be changed. If a “1” is read in the UIP bit,
the time/calendar data may not be valid. The user should
avoid interrupt service routines which would cause the time
needed to read valid time/calendar data to exceed 244.1 μs.
the time and calendar values. All seven timekeeping registers
are clocked by the same internal 1.0 Hz clock, so updates
occur simultaneously, even during rollover. After the counters
are incremented, the current time is compared to the time-of-
day alarm registers 30.5 μs later, and if they match, the AF bit
in register C will be set.
registers are incremented, and ends when the alarm
comparison is complete. During this 30.5 μs update cycle,
the time, calendar, and alarm bytes are fully accessible by the
processor program. If the processor reads these locations
during an update, the transitional output may be undefined.
The update in progress (UIP) status bit is set 244.1 μs before
this interval, and is cleared when the update cycle completes.
Interrupts
interrupts to the processor. The alarm interrupt may be
programmed to occur at a rate of once per day. The update-
ended interrupt may be used to indicate to the program that
an update cycle is completed.
wishes to receive. Two bits in Register B enable the two
56
900841
FUNCTIONAL DEVICE OPERATION
CLOCK GENERATION AND REAL TIME CLOCK (RTC)
The primary function of the update cycle is to increment
Two methods of avoiding undefined output during updates
The first method uses the update-ended interrupt. If
The second method uses the update-in-progress bit (UIP)
The Update-cycle begins when the clock and calendar
The RTC includes two separate, fully automatic sources of
The processor program selects which interrupts, if any, it
The RTC uses seven synchronous counters to increment
interrupts. Writing a “1” to an interrupt-enable bit permits that
interrupt to be initiated when the event occurs. A “0” in the
interrupt-enable bit, prohibits the IRQF bit from being
asserted due to the interrupt cause.
becomes enabled, the IRQF bit is immediately activated,
though the interrupt initiating the event may have occurred
much earlier. Thus, there are cases where the program
should clear such earlier initiated interrupts before enabling
new interrupts.
Register C. Each of the two interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding
enable bits.
enable the interrupt. The interrupt flag bit becomes a status
bit, which the software interrogates when it wishes. When the
software detects the flag is set, it is an indication to the
software an interrupt event occurred since the bit was last
read.
C are cleared (record of the interrupt event is erased) when
Register C is read. Double latching is included with Register
C, so the bits which are set are stable throughout the read
cycle. All bits which are high when read by the program are
cleared, and new interrupts (on any bits) are held until after
the read cycle. One or two flag bits may be found to be set
when Register C is used. The program should inspect all
utilized flag bits every time Register C is read to insure that
no interrupts are lost.
interrupts. When an interrupt flag bit is set and the
corresponding interrupt enable bit is also set, the IRQF bit is
asserted high. IRQF is asserted as long as at least one of the
two interrupt sources has its flag and enable bits both set.
initiated the interrupt by reading Register C. A “1” in bit 7
(IRQF bit) indicates that one or more interrupts have been
initiated by the part. The act of reading Register C clears all
the then active flag bits, plus the IRQF bit. When the program
finds IRQF set, it should look at each of the individual flag bits
in the same byte which have the corresponding interrupt
mask bits set and service each interrupt which is set. Again,
more than one interrupt flag bit may be set.
ALARM INTERRUPT
alarm interrupt. When the program inserts an alarm time in
the appropriate hours, minutes, and seconds alarm locations,
the alarm interrupt is initiated at the specified time each day,
if the alarm enable bit is high.
If an interrupt flag is already set when the interrupt
When an interrupt event occurs, a flag bit is set to a “1” in
In the software scanned case, the program does not
However, there is one precaution. The flag bits in Register
The second flag bit usage method is with fully enabled
The processor program can determine that the RTC
The three alarm bytes may be used to generate a daily
Analog Integrated Circuit Device Data
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