SC900841JVKR2 Freescale Semiconductor, SC900841JVKR2 Datasheet - Page 139

• Manufacturer Part Number: SC900841JVKR2
• Description: IC POWER MGT 338-MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of SC900841JVKR2

• Applications: PC's, PDA's
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 338-TBGA
• Input Voltage: 2.8 V to 4.4 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

D/A CONVERTER
PCM words entering at a rate of 8.0 kHz and 16 kHz into
analog audio signals. Prior to this D/A conversion, the audio
STEREO CODEC
and two 24-bit D/A converters. It supports several different
clocking modes. The stereo DAC and ADC are supplied by
VCORE for its analog and VCOREDIG for its digital sections.
The voice ADC and the stereo ADC use the same converter
Table 85. Voice CODEC D/A Performance Specifications
Analog Integrated Circuit Device Data
Freescale Semiconductor
FILTERING
Notes
Table 84. Voice CODEC A/D Performance Specifications
FILTERING
Notes
Output Range
Absolute Gain
PSRR
THD+N
Idle Channel Noise
Intermodulation Distortion
Crosstalk A/D to D/A
Enable Time
Pass Band
Pass Band Ripple
Stop Band
Stop Band Attenuation
Group Delay
23.
24.
Crosstalk A/D to D/A
Enable Time
Pass Band
Pass Band Ripple
Stop Band
Stop Band Attenuation
Group Delay
The D/A portion of the voice CODEC converts 14-bit linear
The stereo CODEC is based on two 16-bit A/D converters
21.
22.
Equivalent to +3.0 dBm0
Equivalent to 500 mVrms
Equivalent to +3.0 dBm0
Equivalent to 340 mVrms
Parameter
0 dBFS
1.02 kHz, 0 dB Gain
Relative to BP
1.02 kHz, 0 dBm0
0 dB Gain
SMTPE method 50 Hz/1020 Hz,
4:1 0 dBm0 total input level
A/D 1.02 kHz, 0dBm0,
D/A 1.02 kHz, 0dBm0 referred
Including filters
A/D 1.02 kHz, 0 dBm0,
D/A 1.02 kHz, 0 dBm0 referred
Including filters
(23)
Condition
(24)
signal is digitally band-pass filtered. An optional high-pass
filter can also be enabled by setting the VCEAUDHPF bit.
The D/A is enabled by setting the PSCNTRX bit.
cores, so both cannot be used at the same time. The analog
circuits use the REFD bias and the half rail bias at REFA. The
stereo converters incorporate a PLL to generate the proper
clocks. The PLL does not require any external filtering.
at the same sample frequency using the same digital
interface bus. The stereo DAC can be operated in parallel to
Both the stereo ADC and stereo DAC will always operate
0.4535*FS
0.4535*FS
Minimum
-1.0
-0.5
-0.5
80
60
60
Typical
2.3/FS
FUNCTIONAL DEVICE OPERATION
1.7/FS
2.0
-90
3.0
3.0
90
0.5465*FS
Maximum
0.56*FS
-60
-65
-40
-60
0.5
1.0
0.5
dBm0A
Units
ms
dBA
dBA
dB
Hz
dB
Hz
dB
V
ms
AUDIO
dB
dB
dB
Hz
dB
Hz
dB
s
s
900841
PP
139