IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 11

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started with the 10-Gbps Ethernet IP
IP Core Parameterization
Figure 2–2. 10-Gbps Ethernet Parameter Settings
2.2.1. Variation Options
Table 2–1. Variation Options (Part 1 of 2)
© July 2010 Altera Corporation
MAC + XGMII
MAC + XAUI
MAC + Soft XAUI
Parameter Settings
1
Depending on the device and options that you choose, some of the parameters may
not be available.
Table 2–1
describes the variation options available on the Parameter Settings tab.
Creates a IP core with a media access control (MAC) using an Avalon
(Avalon-ST) interface on the client side and 32-bit standard DDR XGMII interface
operating at 156.25 MHz on the network side.
Creates a IP core that combines a MAC and a 10GBASE-X hard macro PHY with
an Avalon-ST interface on the client side and standard XAUI interface on the
network side.
Creates a IP core that has the same functionality and external interfaces as a MAC
with 10GBASE-X hard macro PHY; however, the physical coding sublayer (PCS)
is implemented in soft logic instead of a hard macro.This option is only available
for Stratix IV devices.
Description
Getting Started with the 10-Gbps Ethernet IP
Parameters, EDA Tools
and Summary Tabs
®
Streaming
2–5