IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 38

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–12
Table 3–4. Tx XGMII Interface
10-Gbps Ethernet IP Functional Description
xgmii_tx_clk
xgmii_tx_data[31:0]
xgmii_tx_ctrl[3:0]
Signal Name
Figure 3–11. Tx and Rx XGMII Interface
Notes to
(1) The SYS PLL is not part of the 10-Gbps Ethernet IP core.
(2) The sysclk and the 90° phase shifted clock should come from the same PLL to ensure 0 ppm difference.
Table 3–4
3.2.3.2. SDR XGMII Tx Interface
This interface consists of a 64-bit data bus and 8-bit control bus operating at
156.25 MHz. The data bus carries the MAC frame; the most significant byte occupies
the least significant lane.
Figure
Altera FPGA
Dir
O
O
O
describes the signals that comprise this interface.
3–11:
MAC RX
MAC Tx
Clock with an additional output that has a 90° phase lag with respect to
xgmii_tx_data and xgmii_tx_ctrl signals.
4-lane data bus carrying bytes[7:0] of MAC Tx module changing value on both edges
of xgmii_tx_clk.
4-bit signal that indicates when a control octet is present on the corresponding
xgmii_tx_data lane.
0 degree
rs_tx_dat[63:0]
rs_tx_ctrl[7:0]
rs_tx_dat[63:0]
rs_tx_ctrl[7:0]
SYS PLL (1)
sysclk
90 degree
(SDR or DDR)
Description
Module
XGMII
© July 2010 Altera Corporation
xqmii_rx_clk
xqmii_rx_data[31:0]
xqmii_rx_ctrl[3:0]
xqmii_tx_clk
xqmii_tx_data[31:0]
xqmii_tx_ctrl[3:0]
MAC Functional Description