IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 80

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–54
3.7. 10-Gbps Ethernet PHY
3.7.1. 10GBASE-X PHY
10-Gbps Ethernet IP Functional Description
f
1
1
For Clause 45, follow these steps:
1. Set up the mdio_addr0 register at address 0x03C, where:
2. Read or write the register of the device of the port selected by reading or writing to
Post-read increment is not supported.
3.6.10.4.MDIO Clock Generation
The management data clock (MDC) is generated from the Avalon-MM interface clock
signal, clk.
The division factor must be defined such that the MDC frequency does not exceed
2.5 MHz.
3.6.10.5.MDIO Buffer Connection
Figure 3–29
Figure 3–29. MDIO Buffer Connection
This section provides a high-level description of various PHY options.
You can use the 10GBASE-X PHY to connect a 10-Gbps Ethernet MAC to the physical
media over a four-lane XAUI electrical interface running at 3.125 Gbps. This PHY
consists of a 10GBASE-X PCS and PMA.
this figure shows, the PHY consists of two main parts: a PMA that interfaces to
physical media and the PCS that handles the encoding and decoding necessary to
transport the 10-Gbps Ethernet data on and off the device.
The Altera PHY includes the Altera Transceiver (ALTGXB or ALT2GXB) that includes
the PMA, a selectable hard or soft PCS, and a reset controller block. The reset control
block performs the reset sequence recommended for the ALTGXB megafunction.
For more information on reset refer to the
Volume 2 of the Stratix IV Device Handbook, the “Reset Control and Power Down”
section in Section I of the
Power Down
■
■
■
address 0x320.
Bits 31:16 are the Address
Bits 12:8 are the PRTAD
Bits 4:0 are the DEVAD
illustrates the buffers you can implement for the MDIO tristate bus.
in Volume 2 of the Arria II GX Device Handbook.
Stratix II GX Transceiver User
mdio_oeN
mdio_out
mdio_in
Figure 3–30
Reset Control and Power Down
MDIO
illustrates this configuration. As
Guide, or
© July 2010 Altera Corporation
Reset Control and
10-Gbps Ethernet PHY
chapter in