IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 50

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–24
10-Gbps Ethernet IP Functional Description
The ECC feature changes FIFO entry widths as shown in
Table 3–11. Receive and Transmit FIFO Entries With and Without ECC Bits
In the rate-matching FIFO in the Soft XAUI PCS, the ECC feature changes FIFO entry
widths as shown in
Table 3–12. Soft XAUI Rate-Matching FIFO Entries With and Without ECC Bits
In the per-lane deskew FIFOs in the Soft XAUI PCS, the ECC feature changes FIFO
entry widths as shown in
Table 3–13. Soft XAUI PCS Deskew FIFO Entries With and Without ECC Bits
ECC-detected errors are indicated on the following three output signals:
■
■
■
These signals are asserted for one Avalon-MM clock cycle to indicate a relevant error.
A packet is dropped if an ECC-detected multiple-bit error obscures a valid SOP or
EOP indication. Technically, two packets are merged, resulting in one incorrect packet
in place of two correct packets. In addition, when the IP core detects a multiple-bit
error in a packet, it flags an error by asserting the err bit with the packet in the EOP
cycle.
The Soft XAUI PCS does not report packets dropped, but a packet start or end in a
XAUI FIFO can be corrupted. If a multiple-bit error is detected, the IP core inserts a
disparity error in the FIFO entry, which affects two columns. The IDLE conversion
state machine translates the disparity error to a local fault. If an error occurs during a
frame, the MAC terminates the frame and asserts the ecc_mbe signal.
Turning on the ECC feature instantiates a comprehensive set of error insertion
registers to support error insertion for ECC testing, and a set of statistics counters that
software can read. For more information about these registers, refer to
Monitoring and Testing” on page
Data
Control
Information Type Width Without ECC (bits)
Data
Control
Data
Information Type Width Without ECC (bits)
Information Type Width Without ECC (bits)
ecc_sbe—Single-bit error detected and corrected
ecc_mbe—Multiple-bit error, more specifically a double-bit error, detected
ecc_packet_dropped—Packet was dropped from Rx or Tx FIFO
Table
Table
3–12.
64
18
64
22
8
3–13.
3–44.
Number of ECC Bits
Number of ECC Bits
Number of ECC Bits
8
6
8
5
6
Table
© July 2010 Altera Corporation
Width with ECC (bits)
Width with ECC (bits)
Width with ECC (bits)
3–11.
“ECC
72
24
72
13
28
ECC Options