IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 35

IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design

IP-10GETHERNET

Manufacturer Part Number
IP-10GETHERNET
Description
IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
Manufacturer
Altera
Datasheet

Specifications of IP-10GETHERNET

Software Application
IP CORE, Interface And Protocols, ETHERNET
Supported Families
Quartus II
Core Architecture
FPGA
Core Sub-architecture
Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
MAC Functional Description
Table 3–2. FIFO Thresholds
© July 2010 Altera Corporation
tx_almost_full_on
tx_almost_full_off
tx_almost_empty_on
tx_almost_empty_off
Threshold in Bytes
1
Figure 3–8. FIFO thresholds in Tx FIFO
Notes to
(1) For the Rx FIFO, the write port connects to the MAC and the read port connects to the client.
Table 3–2
3.2.2.5. FIFO MAC Interface
When the client connects to the FIFO, the Tx MAC reads client data from FIFO read
port, updates the data as required, and sends the MAC frame to the PHY interface.
The FIFO provides a continuous stream of bytes to the MAC between the
avl_st_tx_sop
using the avl_tx_read signal indicating when it is ready to receive data. If
avl_tx_read is deasserted, valid data may continue for one cycle.
If your design does not include the FIFO, the client should mimic the FIFO MAC
interface.
Figure
This threshold represents the space available for write data in the FIFO. When almost full,
the avl_st_tx_dav signal is deasserted, indicating that the client should stop sending
data to FIFO.
This threshold represents the space that must be available in the FIFO before client data can
be written in the FIFO. When this condition occurs, avl_st_tx_dav is asserted enabling
the client transmission. The tx_almost_full_off must be >=
tx_almost_full_on.
This threshold represents the number of bytes available for read before the FIFO is empty.
When this condition occurs, the avl_tx_dav signal is deasserted indicating no data is
available for the Tx MAC.
This represents the amount of data that must be available in the FIFO before reads can
resume. When this condition occurs avl_tx_dav is asserted indicating the availability of
data for read. tx_almost_empty_off must be >= tx_almost_empty_on.
explains these thresholds.
3–8:
and avl_st_tx_eop signals. The Tx MAC can apply backpressure
(space available)
avl_st_tx_dav
Client Side
Write Port
tx_almost_full_off
tx_almost_empty_off
tx_almost_empty_on
tx_almost_full_on
Description
10-Gbps Ethernet IP Functional Description
(data available)
user_tx_dav
Read Port
MAC Side
3–9

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