IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 70

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–44
3.6.8. ECC Monitoring and Testing
Table 3–23. ECC Management Registers Memory Map (Part 1 of 2)
10-Gbps Ethernet IP Functional Description
0x350
0x354
0x358
0x35C
0x360
0x364
0x368
0x36C
0x370
0x374
0x378
0x37C
Address
1
If you perform a read access to an address other than the upper 32 bits after reading
the lower part, the cached value may be lost. If an upper 64-bit register is read without
accessing the lower 32 bits first, the stored value is given (not the cached value).
The 10-Gbps Ethernet IP core ECC feature implements single-bit error correction and
double-bit error detection (SECDED). The ECC management registers support ECC
monitoring and testing by error injection. Single-event memory errors are infrequent,
and extremely unlikely to occur during testing without error injection. The ECC
management registers support software testing of the optional ECC feature, and also
provide cumulative statistics counters for ECC-detected errors.
The following sections describe the ECC management registers and how the IP core
implements ECC testing based on the values in these registers.
3.6.8.1. ECC Management Registers
If you turn on ECC Protected RAMs in the MegaWizard interface, and the MAC is
instantiated, the ECC testing registers and ECC statistics counters are implemented in
the 10-Gbps Ethernet IP core. Because the ECC management registers are available
only if the MAC is instantiated, they are not available in Soft XAUI only mode.
However, in Soft XAUI only mode, special input signals allow software to specify Soft
XAUI error injection to the IP core. Therefore, in this case you can test the ECC
feature, even though the IP core does not maintain ECC testing registers or
cumulative statistics information.
The ECC statistics counters are cleared upon read (RC). Their implementation is
based on an assumption that single-event errors are rare. The statistics registers might
not provide an accurate count if two errors occur less than 10 clock cycles apart, or if
two different blocks attempt to increment a register simultaneously.
Table 3–23
through
feature, and
Reserved
ECC_FIFO_INS
ERR_FIFO_TX_DATA_ECC_0
ERR_FIFO_TX_DATA_ECC_1
ERR_FIFO_TX_DATA_ECC_2
ERR_FIFO_TX_CTRL_ECC
ERR_FIFO_RX_DATA_ECC_0
ERR_FIFO_RX_DATA_ECC_1
ERR_FIFO_RX_DATA_ECC_2
ERR_FIFO_RX_CTRL_ECC
Reserved
ECC_XAUI_INS
Table 3–41
provides a memory map for the ECC management registers.
Table 3–42
Name
describe the registers that support software testing of the ECC
through
Table 3–51
FIFO Errors Insert
Tx FIFO Data Errors Word 0
Tx FIFO Data Errors Word 1
Tx FIFO Data Errors Word 2
Tx FIFO Control Errors
Rx FIFO Data Errors Word 0
Rx FIFO Data Errors Word 1
Rx FIFO Data Errors Word 2
Rx FIFO Control Errors
Soft XAUI PCS Errors Insert
describe the ECC statistics counters.
Expanded Name
© July 2010 Altera Corporation
Register Descriptions
Table 3–24