IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 32

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–6
3.2.2. Tx Interfaces
10-Gbps Ethernet IP Functional Description
f
1
The deficit idle counter maintains an average IPG. You can configure the average IPG
value in the tx_ipg_length register (0x05c). The number is a multiple of 4 with a
minimum of 8 and a maximum of 252. The default (IEEE required value) is 12.
To guarantee reliable PCS functionality, Altera recommends that you set the IPG to a
minimum of 12 bytes. The IPG between successive frames varies and is the minimum
that you specify
This section describes the following Tx interfaces:
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3.2.2.1. Tx Client Side Interfaces
The client side of the interface depends on whether you included a FIFO in your
design. If a FIFO is included, the client connects to the FIFO’s client side interface,
otherwise the client connects directly to the MAC’s client interface.
The client Tx datapath employs the Avalon Streaming (Avalon-ST) protocol. The
Avalon-ST protocol is a synchronous point-to-point, unidirectional interface that
connects the producer of a data stream (source) to a consumer of data (sink). The key
properties of this interface include:
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The client acts as a source and the Tx FIFO/MAC acts as a sink in the transmit
direction. If your design does not include the optional FIFO, the MAC does not buffer
client data and it must receive data continuously between the assertions of the
startofpacket and endofpacket signals.
For more information about the Avalon-ST interface refer to the
Specifications.
3.2.2.2. Tx FIFO Client Interface
This is an Avalon-ST interface that provides backpressure from the MAC Tx sink to
the client via Tx FIFO. The Tx FIFO receives data from the client and buffers it until
the MAC is ready to consume it.
“Tx Client Side Interfaces ” on page 3–6
“Tx FIFO Client Interface ” on page 3–6
“FIFO MAC Interface ” on page 3–9
“SDR XGMII Tx Interface ” on page 3–12
“Standard DDR XGMII Interface” on page 3–11
Frame transfers marked by startofpacket and endofpacket signals.
Signals from source to sink are qualified by the valid signal.
Errors marking a current packet, are aligned with endofpacket cycle.
Use of the ready signal by the sink backpressure the source. The source must
respond to the ready signal from sink by deasserting the valid signal after a
fixed number of cycles defined by the ready_latency.
±
3 bytes.
Figure 3–6
illustrates this interface.
© July 2010 Altera Corporation
MAC Functional Description
Avalon Interface