IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 77

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Register Descriptions
3.6.10.MDIO External PHY Management Interface
© July 2010 Altera Corporation
The Soft XAUI PCS rate-matching FIFO might skip a write during rate compensation.
In that case, a bit error is inserted in the following write. A bit error inserted during an
idle cycle might cause the MAC to ignore the next packet or insert an error in the
previous packet. The Soft XAUI PCS cannot signal a dropped packet using the
ecc_packet_dropped signal.
The MDIO interface is a two-wire standard management interface that implements a
standardized method to access the external PHY device management registers. The IP
core MDIO interface supports IEEE 802.3 Clause 22 (see
The PHY device MDIO registers are mapped in the register space and can be read and
written from the Avalon-MM interface. The IP core provides the flexibility to access
PHY devices with the MDIO address set to any legal value.
Figure 3–28. MDIO Interface (Clause 22)
Management
MDIO Frame
Management
MDIO Frame
Generation
Generation
Registers
Decoding
Registers
Decoding
0 to 31
0 to 31
PHY
And
PHY
And
PHY Device
PHY Device
Interface
Address
Interface
Address
Parallel-
Parallel-
Serial
PHY
Serial
PHY
to-
to-
MDC
MDIO
Avalon-MM Interface
Ethernet Reference
10-Gbps Ethernet IP Functional Description
MDIO Frame
Generation
Figure
Decoding
10-Gbps
Interface
Register
Design
And
3–28) and Clause 45.
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