IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 4

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–2
1.2. Performance and Resource Utilization
Table 1–1. 10-Gbps Ethernet Performance and Resource Utilization—Stratix II GX Device
10-Gbps Ethernet IP Datasheet
XAUI
Yes
Yes
Yes
Yes
(eight-
words)
FIFO
byte
256
256
256
No
MDIO
Yes
Yes
No
No
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Table 1–1
configurations and parameters, using the Quartus II software version 9.1 targeting a
Stratix II GX (EP2SGX30DF780C3) device.
For C4 and C5 device speed grades the f
Automatic or host-controlled flow control frame transmission can be initiated by
either the host using explicit signals or by the host using configuration register.
The xon_req and xoff_req signals can be controlled by either the MAC client or
by the host via the configuration registers.
Programmable pause quanta.
Parameterizable FIFO size (64 bytes to 64 Kbytes) and programmable threshold
levels.
Programmable MAC addresses and receive packet filtering based on up to five
unicast or multicast and broadcast destination MAC addresses.
Programmable maximum receiving frame length up to 64 KBytes, including
jumbo frames (1,519 to 9,618 bytes).
Support for promiscuous (transparent) and non-promiscuous (filtered) modes of
operation.
Support for virtual LAN (VLAN) and stacked VLAN tagged frames according to
the IEEE 802.1Q and 802.1ad (QinQ) standards, respectively.
Remote (Line) and Local (Client) loopback at XGMII for system test.
Statistics counters supporting RMON (RFC 2819), Ethernet type MIB (RFC 3635),
and interface group MIB (RFC 2863).
Programmable filtering of received frames with CRC errors, length-check error, or
oversized errors.
Easy-to-use MegaWizard
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators.
Verilog HDL and VHDL testbench and verification environment.
Deficit Idle Count (DIC) is supported
Statistics
Counter
Yes
No
No
No
shows the typical expected device resource utilization for different IP
ECC
No
No
No
No
Combinational
ALUTs
3,246
3,652
3,803
5,666
TM
GUI for IP parameterization and generation.
Registers
Logic
3,238
3,654
3,788
5,334
MAX
is 156.25 MHz.
Avalon
-MM
156
174
170
189
f
MAX
Avalon
Performance and Resource Utilization
199
200
218
-ST
—
(MHz)
© July 2010 Altera Corporation
System
Clock
202
179
187
204
M4K M512
0
8
8
8
Memory
0
0
0
0