IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 83

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Clocks and Reset
3.8. Clocks and Reset
3.8.1. MAC, PHY Resets and Clocks
Figure 3–31. MAC, PHY Resets and Clocks
© July 2010 Altera Corporation
reset_n
avl_st_reset_n
avl_st_tx_clk
avalon addr & data
avalon_clk
avalon_reset_n
sysclk (pll_inclk)
cal_blk_clk
reconfig_clk
serdes_sysclk
The clocking depends upon the variant you specify. The IP core includes at least three
clock domains. A fourth clock domain controls the ALTGX_RECONFIG
megafunction. The following sections illustrate the clock domains for the different
configurations.
In this configuration, the PHY provides a clock that can be used for MAC and MAC
side of the FIFO logic, as
Altera FPGA with Internal Transceivers
Avalon-ST clock domain (avl_st_tx_clk )
Avalon-MM clock domain (avalon_clk)
Sysclk domain (serdes_sysclk or coreclkout)
Rx recovered clock domain, not available to user
FIFO
FIFO
Wr
Wr
Interface
Avalon
FIFO
FIFO
Rd
Rd
Static register bits
Figure 3–31
MAC Rx
MAC Tx
Sync
XGMII-like IF
Dynamic register bits (sysclk)
64-bit SDR
illustrates.
coreclock_out
FIFO
Rd
10-Gbps Ethernet IP Functional Description
Tx PCS & PMA
FIFO
Wr
PHY
PCS & PMA
Rx
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