IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 25

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started with the 10-Gbps Ethernet IP
Implementation and Timing Analysis
Example 2–2. Timing Constraints for the 10-Gbps Ethernet IP Core
// Create clocks other than generated clocks
create_clock -period 6.4 -name {sysclk} [get_ports *sysclk]
create_clock -period 10 -name {avalon_clk} [get_ports *avalon_clk]
create_clock -period 6.4 -name {avl_st_clk} [get_ports *avl_st_clk]
create_clock -period 20 -name {reconfig_clk} [get_ports *reconfig_clk]
// Create asynchronous clock groups
set_clock_groups -asynchronous -group {sysclk} –group {avalon_clk }
set_clock_groups -asynchronous -group {avl_st_clk} –group {avalon_clk}
set_clock_groups -asynchronous -group { avalon_clk } -group
{*eth_10g_inst|xaui_10g__genblk.xaui_10g|xaui_10g_serdes4_reconfig__genblk.xaui_10g_se
rdes4_reconfig|xaui_10g_serdes4_reconfig_*|central_clk_div0|coreclkout }
set_clock_groups -asynchronous -group { avl_st_clk } -group {
*eth_10g_inst|xaui_10g__genblk.xaui_10g|xaui_10g_serdes4_reconfig__genblk.xaui_10g_ser
des4_reconfig|xaui_10g_serdes4_reconfig_*|central_clk_div0|coreclkout }
2.5.4. Placement Constraints
Example 2–3. Pin Assignments in the .qsf File
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" –to MYPIN
set_location_assignment PIN_G14 -to MYPIN
2.5.5. Timing Verification
Table 2–7. Quartus II Output Files
© July 2010 Altera Corporation
<variation_name>.pin
<variation_name>.fit.rpt
<variation_name>.sta.rpt
File Name
f
Example 2–2
core.
Refer to
In this example, some global clocks and synthesis options are specified in
tge_constraints.tcl.
Refer to the appropriate
Device Pin Connection Guidelines
determine available I/O standards and pin assignments for your design.
Upon successful compilation, the Quartus II software generates output files that
specify important features of your design.
files. All of the output files are described in <variation_name>.html.
“Clocks and Reset ” on page 3–57
Lists the pin location assignments in the final design.
Contains information on logic utilization, resource utilization, timing models, and
other useful information.
Provides the timing analysis report and the results of the timing analysis including
timing path slack.
shows the constraints included in the .sdc for the 10-Gbps Ethernet IP
Example 2–3
Device Handbook, Pin-Out Files for Altera
shows typical pin type and placement assignments.
web pages for the targeted Altera device to
Table 2–7
for more information about clocking.
Description
lists the most important output
Getting Started with the 10-Gbps Ethernet IP
Devices, and
2–19