IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 62

IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design

IP-10GETHERNET

Manufacturer Part Number
IP-10GETHERNET
Description
IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
Manufacturer
Altera
Datasheet

Specifications of IP-10GETHERNET

Software Application
IP CORE, Interface And Protocols, ETHERNET
Supported Families
Quartus II
Core Architecture
FPGA
Core Sub-architecture
Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
3–36
Table 3–16. Control Interface Register Map (Part 5 of 7)
10-Gbps Ethernet IP Functional Description
0x200
0x27C
0x280
0x2FC
0x300
0x304
0x308
0x30C
0x310
Address
Offset
PHY Device 0 Internal Registers
Reserved
smac_0_0
smac_0_1
smac_1_0
smac_1_1
smac_2_0
Name
Registers 0–31 within PHY device 0
connected to the MDIO PHY
management interface. Reading or
writing immediately causes the
corresponding MDIO transaction to
read or write the underlying PHY
device register.
The register at address offset 0x200
corresponds to register 0 of PHY
device 0. The register at address
offset 0x204 corresponds to register
1 of PHY device 0.
For all registers, bits 15:0 are
significant. Bits 31:16 should be
written with 0 and ignored on read.
Reserved.
Supplemental address 0, bits 31:0.
Register bit 0 maps to bit 0 of the
address, bit 1 maps to bit 1 of the
address, and so on.
Supplemental address 0, bits 47:32.
Register bit 0 maps to bit 32 of the
address. Register bits 30:16 are
reserved. register bit 31 enables
address:
Supplemental address 1, bits 31:0.
Register bit 0 maps to bit 0 of the
address, bit 1 maps to bit 1 of the
address, and so on.
Supplemental address 1, bits 47:32.
Register bit 0 maps to bit 32 of the
address. Register bits 30:16 are
reserved. register bit 31 enables
address:
Supplemental address 2, bits 31:0.
Register bit 0 maps to bit 0 of the
address, bit 1 maps to bit 1 of the
address, and so on.
0 to disable
1 to enable
0 to disable
1 to enable
Description
Access
RW
RW
RW
RW
RW
RW
RO
© July 2010 Altera Corporation
HW Reset
0
0
0
0
0
0
0
Register Descriptions
SW Reset

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