IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 86

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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Table 3–57. Clock Signals (Part 2 of 2)
avalon_clk
avl_st_clk
xgmii_rx_clk
xgmii_tx_clk
serdes_sysclk
phy_mdc
cal_blk_clk
Signal
For the definition of reconfig_clk, refer to
page
The Avalon-MM clock that controls the Avalon-MM interface used for statistics and configuration.
This clock can be shared with other modules, an SOPC system, or can be tied to the system clock.
Avalon-ST clock input for the datapath, which can be different if a FIFO is present. This clock can
be tied to the system clock.
Captures the data arriving on the XGMII Rx interface, a PLL and local clock are required. The
incoming clock is shifted by 90 degrees to capture the data.
Clock that accompanies xgmii_tx_data and xgmii_tx_ctrl. It is shifted by 90
respect to xgmii_tx_data and xgmii_tx_ctrl.
XAUI clock. When using the XAUI block, the transceiver module has its own PLL to derive the
required output clocks. You can feed both the Tx and Rx data clock, which are connected to the
system clock, and the clock domain crossing from network clock to system clock occurs within
the transceiver block.
MDIO clock. The frequency of the MDIO must be less than 2.5 MHz and is derived from the
Avalon-MM clock. the MDIO clock cannot be shared between modules.
SERDES calibration clock. The frequency of this clock should be between 10–125 MHz.
3–55.
Description
“Top-Level Transceiver Signals” on
.
°
with