IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 36

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–10
Table 3–3. FIFO or Client MAC Interface Signals (Part 1 of 2)
10-Gbps Ethernet IP Functional Description
user_tx_dat[63:0]
user_tx_data_valid
user_tx_sop
user_tx_eop
user_tx_mty[2:0]
user_tx_dav
Signal Name
Figure 3–8
Figure 3–9. FIFO MAC Tx Interface
Table 3–3
Dir
Client or FIFO
I
I
I
I
I
I
TX Interface
describes the signals that comprise this interface.
illustrates the FIFO MAC Tx interface.
64-bit client or source data.
When asserted, Indicates that the rest of the MAC inputs are valid.
Asserted for _one cycle to indicate the start of client/source data.
Asserted for one cycle to indicate the end of client/source data.
Specifies how many bytes of user_tx_dat[63:0] are empty when
user_tx_eop is asserted as follows:
Value
0
1
2
3
4
5
6
7
Indicates that the source has data available for the MAC’s consumption. This signal
should only be asserted when the source has an entire frame for the MAC or is
guaranteed to send the entire packet once the MAC starts requesting data. If your
variant includes the optional FIFO, the FIFO drives user_tx_dav, otherwise, the
client interface drives user_tx_dav.
FIFO
Tx
Valid Data Bits
user_tx_dat[63:0]
user_tx_dat[63:8]
user_tx_dat[63:16]
user_tx_dat[63:24]
user_tx_dat[63:32]
user_tx_dat[63:40]
user_tx_dat[63:48]
user_tx_dat[63:56]
user_tx_err
user_tx_dat[63:0]
user_tx_data_valid
user_tx_sop
user_tx_eop
user_tx_mty[2:0]
user_tx_dav
user_tx_read
Description
MAC
Tx
© July 2010 Altera Corporation
MAC Functional Description
Tx Interface
PHY MAC